The present invention relates generally to the field of semiconductor devices, and more particularly to FINFET semiconductor structures.
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques, and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
A metal oxide semiconductor field-effect transistor (MOSFET) has been the building block for most computing devices for the last several decades. A MOSFET is a four terminal device made up of a drain, a source, a gate and a bulk substrate. In digital circuits, the MOSFET is essentially used as a switch. The source and drain are two ends of the switch, with the channel being turned on and off under the control of the gate. The gate controls the conductivity through the channel through an electric field and is insulated from the channel by a thin layer of dielectric material, such as silicon dioxide. With no voltage potential across the gate and bulk, a depletion region forms around the drain and source blocking any current flow.
The MOSFET has been the primary building block of integrated circuits for more than forty years. The advances in electronics have been driven primarily by the ability to scale down the size of the MOSFETs used in integrated circuits. This scaling achieves improvements on many fronts. Smaller transistors allow more transistors to be put on the same size chip, which has allowed integrations levels to rise from the hundreds of transistors to hundreds of millions of transistors.
With the continuous reduction of surface area in a semiconductor wafer available for a single semiconductor device, engineers are faced with the challenge of ever increasing device density. For sub-80 nm pitch patterning, one technique is to achieve twice the pattern density through a technique called sidewall imaging transfer (SIT), which is also known as sidewall spacer image transfer. In a conventional SIT process, a blanket deposition of spacer making material, such as dielectric material, is usually performed after the mandrel lithography development and spacers are then made out of the blanket layer of spacer making material through a directional etching process.